Direct Memory Entry
Without DMA, when the CPU is utilizing programmed input/output, it is typically fully occupied for the complete duration of the read or write operation, and is thus unavailable to carry out other work. With DMA, the CPU first initiates the switch, then it does different operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller (DMAC) when the operation is completed. This feature is helpful at any time that the CPU can not keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a comparatively sluggish I/O knowledge switch. Many hardware programs use DMA, together with disk drive controllers, graphics playing cards, community cards and sound playing cards. DMA can also be used for intra-chip information transfer in some multi-core processors. Computer systems that have DMA channels can transfer information to and from gadgets with much much less CPU overhead than computer systems with out DMA channels. Similarly, a processing circuitry inside a multi-core processor can transfer data to and from its native memory with out occupying its processor time, allowing computation and information transfer to proceed in parallel.
DMA can also be used for "memory to memory improvement solution" copying or moving of knowledge inside memory. DMA can offload expensive memory operations, equivalent to massive copies or scatter-gather operations, from the CPU to a devoted DMA engine. An implementation instance is the I/O Acceleration Technology. DMA is of curiosity in community-on-chip and in-memory computing architectures. Commonplace DMA, also known as third-celebration DMA, makes use of a DMA controller. A DMA controller can generate memory addresses and initiate memory read or write cycles. It incorporates several hardware registers that can be written and read by the CPU. These include a memory handle register, a byte depend register, and one or more control registers. Depending on what options the DMA controller gives, these control registers may specify some combination of the supply, the destination, the route of the transfer (reading from the I/O system or writing to the I/O machine), the dimensions of the switch unit, and/or the number of bytes to switch in a single burst.
To carry out an enter, output or memory-to-memory operation, the host processor initializes the DMA controller with a depend of the number of words to switch, memory improvement solution and the memory address to use. The CPU then commands the peripheral system to initiate a knowledge switch. The DMA controller then supplies addresses and read/write control strains to the system memory. Every time a byte of information is ready to be transferred between the peripheral machine and memory, the DMA controller increments its inner address register until the full block of knowledge is transferred. Some examples of buses using third-occasion DMA are PATA, USB (before USB4), and SATA; however, their host controllers use bus mastering. In a bus mastering system, also referred to as a primary-party DMA system, the CPU and peripherals can each be granted management of the memory bus.
